Patterned gate dielectrics for iii-v-based cmos circuits

ABSTRACT

Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A gate dielectric layer is formed over one or more of the first and second channel regions. A nitrogen-containing layer is formed on the gate dielectric layer. A gate is formed on the gate dielectric.

BACKGROUND Technical Field

The present invention relates to semiconductor devices and, moreparticularly, to the use of III-V-type and IV-type semiconductor deviceson a single chip.

Description of the Related Art

III-V compound semiconductors, such as gallium arsenide, indium galliumarsenide, indium arsenide, and indium antimonide, may be used intransistor devices using complementary metal oxide semiconductor (CMOS)processes. While such devices have been shown, it is challenging to formIII-V-based devices on the same chip as IV-based devices.

One challenge arises due to the relative volatility of III-Vsemiconductors. Whereas IV-type semiconductors (such as, e.g., siliconand silicon germanium) are stable at high temperatures, III-V-typesemiconductors may be damaged by high-temperature processes thatconventional semiconductors would withstand.

One conventional approach is to use stacked, three-dimensional CMOSdevices, with n-type field effect transistors (FETs) and p-type FETs onseparate layers. Such approaches can provide III-V-based devices andIV-based devices on the respective layers, but the cost may beprohibitively high and it can be difficult to achieve high performanceand reliability due to the complicated fabrication processes.

Another conventional approach uses IV-based p-type FETs and III-V-basedn-type FETs on a given chip, but with the same gate dielectric for each.This does not provide the ability to separately optimize the gate stackproperties (such as, e.g., leakage, threshold voltage, performance,reliability, etc.) of each device type.

SUMMARY

A method for forming a plurality of semiconductor devices includesforming a first channel region on a first semiconductor region. A secondchannel region is formed on a second semiconductor region, the secondsemiconductor region being formed from a semiconductor material that isdifferent from a semiconductor material of the first semiconductorregion. A gate dielectric layer is formed over one or more of the firstand second channel regions. A nitrogen-containing layer is formed on thegate dielectric layer. A gate is formed on the gate dielectric.

A semiconductor device includes a first channel region formed from afirst semiconductor material. A second channel region is formed from asecond semiconductor material, different from the first semiconductormaterial. There is a nitrogen-containing layer on one or more of thefirst and second channel regions. A gate is formed over thenitrogen-containing layer.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The disclosure will provide details in the following description ofpreferred embodiments with reference to the following figures wherein:

FIG. 1 is a cross-sectional diagram of a step in forming a plurality ofsemiconductor devices in accordance with the present principles;

FIG. 2 is a cross-sectional diagram of a step in forming a plurality ofsemiconductor devices in accordance with the present principles;

FIG. 3 is a cross-sectional diagram of a step in forming a plurality ofsemiconductor devices in accordance with the present principles;

FIG. 4 is a cross-sectional diagram of a step in forming a plurality ofsemiconductor devices in accordance with the present principles;

FIG. 5 is a cross-sectional diagram of a step in forming a plurality ofsemiconductor devices in accordance with the present principles;

FIG. 6 is a cross-sectional diagram of a step in forming a plurality ofsemiconductor devices in accordance with the present principles;

FIG. 7 is a cross-sectional diagram of a step in forming a plurality ofsemiconductor devices in accordance with the present principles;

FIG. 8 is a block/flow diagram of a method of forming a plurality ofsemiconductor devices in accordance with the present principles;

FIG. 9 is a cross-sectional diagram of an alternative step in forming aplurality of semiconductor devices in accordance with the presentprinciples;

FIG. 10 is a cross-sectional diagram of an alternative step in forming aplurality of semiconductor devices in accordance with the presentprinciples;

FIG. 11 is a cross-sectional diagram of an alternative step in forming aplurality of semiconductor devices in accordance with the presentprinciples;

FIG. 12 is a cross-sectional diagram of an alternative step in forming aplurality of semiconductor devices in accordance with the presentprinciples;

FIG. 13 is a cross-sectional diagram of an alternative step in forming aplurality of semiconductor devices in accordance with the presentprinciples;

FIG. 14 is a cross-sectional diagram of an alternative step in forming aplurality of semiconductor devices in accordance with the presentprinciples;

FIG. 15 is a block/flow diagram of an alternative method of forming aplurality of semiconductor devices in accordance with the presentprinciples;

FIG. 16 is a cross-sectional diagram of an alternative step in forming aplurality of semiconductor devices in accordance with the presentprinciples;

FIG. 17 is a cross-sectional diagram of an alternative step in forming aplurality of semiconductor devices in accordance with the presentprinciples;

FIG. 18 is a cross-sectional diagram of an alternative step in forming aplurality of semiconductor devices in accordance with the presentprinciples; and

FIG. 19 is a block/flow diagram of a method of forming a plurality ofsemiconductor devices in accordance with the present principles.

DETAILED DESCRIPTION

Embodiments of the present invention provide III-V-based devices andIV-based devices on the same chip using complementary metal oxidesemiconductor (CMOS) processes. Furthermore, the present embodimentsprovide nitride layers on, for example, the semiconductor channelregions of one or both of the III-V-based and IV-based devices.

The most common type of semiconductor devices are based on group IVsemiconductors. These semiconductors include, e.g., silicon (includingpolysilicon, epitaxially grown silicon, and amorphous silicon),germanium, silicon germanium, silicon carbide, and layers thereof. Inaddition, semiconductor devices may be formed using composite III-Vsemiconductors, which use one or more elements from group III on theperiodic table and one or more elements from group V.

Typically, the III-V compound semiconductors are binary, ternary orquaternary alloys including III/V elements. Examples of III-V compoundsemiconductors that can be used in the present embodiments include, butare not limited to aluminum antimonide, aluminum arsenide, aluminumnitride, aluminum phosphide, gallium arsenide, gallium phosphide, indiumantimonide, indium arsenic, indium nitride, indium phosphide, aluminumgallium arsenide, indium gallium phosphide, aluminum indium arsenic,aluminum indium antimonide, gallium arsenide nitride, gallium arsenideantimonide, aluminum gallium nitride, aluminum gallium phosphide, indiumgallium nitride, indium arsenide antimonide, indium gallium antimonide,aluminum gallium indium phosphide, aluminum gallium arsenide phosphide,indium gallium arsenide phosphide, indium arsenide antimonide phosphide,aluminum indium arsenide phosphide, aluminum gallium arsenide nitride,indium gallium arsenide nitride, indium aluminum arsenide nitride,gallium arsenide antimonide nitride, gallium indium nitride arsenidealuminum antimonide, gallium indium arsenide antimonide phosphide, andcombinations thereof.

The use of III-V semiconductors may be advantageous for some purposes,as they provide greater freedom to the circuit designer in selecting theparticular device properties desired for an application. However, whilethe processes for fabricating devices based on group IV semiconductorsare well developed, with many existing fabrication plants using suchprocesses, the processes for fabricating III-V-based devices arerelatively immature. The present embodiments therefore integrate bothtypes of device on a single chip to take advantage of existing IV-typeprocesses.

Referring now to the drawings in which like numerals represent the sameor similar elements and initially to FIG. 1, a step in fabricating a setof field effect transistors is shown. A substrate is shown that includesan insulator layer 102 and a semiconductor layer 104. This embodimentspecifically contemplates a semiconductor-on-insulator (SOI) substratestructure, it should be understood that other types of substrate, suchas a bulk semiconductor substrate, may be used instead.

The insulator layer 102 may be any appropriate insulator or dielectricmaterial. In specific embodiment the insulator layer 102 may be silicondioxide, but other examples include a glass layer, a polyimide layer, adiamond-like carbon layer, etc. The semiconductor layer is specificallycontemplated to be a group IV semiconductor, such as silicon germanium.It should be recognized that any appropriate group IV semiconductor maybe employed, with examples including silicon (polysilicon, epitaxiallygrown silicon, or amorphous silicon), germanium, silicon carbide, andlayers thereof. In an alternative embodiment, the semiconductor layer104 may be a III-V semiconductor material, with indium gallium arsenidebeing specifically contemplated.

Referring now to FIG. 2, a step in fabricating a set of field effecttransistors is shown. A region 202 of contrasting semiconductor materialis formed. In one particular embodiment, it is contemplated that atrench may be formed in the semiconductor layer 104 and the contrastingsemiconductor region 202 may be grown or otherwise deposited in thetrench. In another embodiment, the contrasting semiconductor region 202may be grown or otherwise deposited on the top surface of thesemiconductor layer 104. The formation of the contrasting semiconductorregion 202 may be performed using, e.g., epitaxial growth.

The terms “epitaxial growth and/or deposition” means the growth of asemiconductor material on a deposition surface of a semiconductormaterial, in which the semiconductor material being grown hassubstantially the same crystalline characteristics as the semiconductormaterial of the deposition surface. The term “epitaxial material”denotes a material that is formed using epitaxial growth. In someembodiments, when the chemical reactants are controlled and the systemparameters set correctly, the depositing atoms arrive at the depositionsurface with sufficient energy to move around on the surface and orientthemselves to the crystal arrangement of the atoms of the depositionsurface. Thus, in some examples, an epitaxial film deposited on a {100}crystal surface will take on a {100} orientation.

In a first embodiment, the semiconductor layer 104 is a group IVsemiconductor, such as silicon germanium, and the contrastingsemiconductor region is a III-V semiconductor, such as indium galliumarsenide. In an alternative embodiment, the semiconductor layer 104 isthe III-V semiconductor and the contrasting semiconductor region 202 isthe group IV semiconductor. In either case, both types of semiconductorare present on the same chip.

Although the present embodiments are described with a second channelregion being formed in the substrate semiconductor layer 104 itself, analternative embodiment may have a second contrasting semiconductorregion deposited on or in the substrate semiconductor layer 104. In suchan embodiment, the substrate semiconductor layer 104 may be, forexample, silicon, while the second contrasting semiconductor region maybe, for example, silicon germanium or some other group IV semiconductor.

Referring now to FIG. 3, a step in fabricating a set of field effecttransistors is shown. Doped source/drain regions 302 are formed in thecontrasting semiconductor region 202. Additional doped source/drainregions 304 are formed elsewhere on the semiconductor layer 104. Thefirst set of doped source/drain regions 302 on the contrastingsemiconductor region 202 establish a first channel region 303 betweenthem, while the second set of doped source/drain regions 304 on thesemiconductor layer 104 define a second channel region 306 between them.Notably the first and second channel regions 303/306 are coplanar withone another, defined herein to mean within about 20 nm of verticaldisplacement with respect to one another.

The source/drain regions 302 and 304 can be formed by any appropriateprocess. In one particular example, a dummy gate may be formed to definethe channel regions 303 and 306, with dopant implantation beingperformed at the sides of the dummy gate. The dummy gate maysubsequently be removed to form the actual gates, as is discussed ingreater detail below. It should be noted that the depicted structure ofthe source/drain regions 302 and 304 is meant to be illustrative andshould not be construed as limiting—any structure for the source/drainregions 302/304, including raised source drain regions, mergedsource/drain regions, fin source/drain regions, etc. may be used.

It is specifically contemplated that the first source/drain regions 302and the second source/drain regions 304 may have different respectivedopant types. In particular, it is contemplated that one set of regionswill be p-type and the other will be n-type. In one particularembodiment, it is contemplated that the group IV semiconductorsource/drain regions will be p-type doped, while the III-V semiconductorsource/drain regions will be n-type doped.

The dopant atoms in the respective source/drain regions 302 and 304 maybe an n-type dopant (i.e., an element from Group IV or VI of thePeriodic Table of Elements) or a p-type dopant (i.e., an element fromGroup II or VI of the Periodic Table of Elements). Exemplary n-typedopants for a group IV semiconductor include phosphorus, arsenic andantimony. Exemplary p-type dopants for a group IV semiconductor includeboron, aluminum, and gallium. Exemplary n-type dopants for a III-Vsemiconductor include selenium, tellurium, silicon, and germanium.Exemplary p-type dopants for a III-V semiconductor include beryllium,zinc, cadmium, silicon, and germanium. The concentration of dopantwithin the doped region is typically from about 1011 to about 1015atoms/cm2, with a concentration of dopant within the doped region fromabout 1011 to about 1013 atoms/cm2 being more typical. The source/drainregions 302 and 304 may be doped through an implantation process or may,alternatively, be grown on the underlying layer and doped in situ.

To this point, each of the present embodiments share the same structureand process. The present embodiments diverge, however, regarding theapplication of a nitrogen-containing region over the channels 303 and306. In one embodiment, a nitrogen-containing region is formed over bothchannels, in a second embodiment the nitrogen-containing region isformed over only one type of device, and in a third embodiment thenitrogen-containing region is formed as part of a gate dielectric.

Referring now to FIG. 4, a step in fabricating a set of field effecttransistors is shown. The surfaces may be cleaned with a compatible wetclean to remove, e.g., adventitious contaminants (organics, metals,particles, etc.). The wet clean removes any native oxides that may haveformed on the surfaces that would result in poorly controlled thicknessand composition of the gate dielectrics. The wet clean may includeapplication of dilute hydrofluoric acid, followed by hydrochloric acidfor indium gallium arsenide and silicon germanium channels. Respectivenitrogen-containing layers 402 and 404 are formed on a top surface ofboth the semiconductor channel 306 and the contrasting semiconductorchannel 303. The nitrogen-containing layers 402/404 may be formed using,e.g., an ammonia anneal, nitrogen plasma, etc. In one embodiment, mask406 is deposited over the device, with gaps over the semiconductorchannel 306 and the contrasting semiconductor channel 303, to limit theeffect of the nitrogen-containing layer formation to only the channelareas. The mask 406 may be formed by any appropriate dielectric orinsulator material, such as a hardmask material or bulk dielectric.Materials for the mask 406 may include, e.g., silicon dioxide or siliconnitride. It should be understood that the mask 406 may have anyappropriate shape, leaving areas other than just the channels 303 and306 uncovered. In an alternative embodiment, the mask 406 may be omittedentirely, with the nitrogen-containing region being formed on arbitraryregions and later being removed as needed.

In one embodiment, the nitrogen-containing layer 402/404 may be anitrogen monolayer or other thing layer of nitrogen-containing materialthat adheres to the surface of the channels 303/306.

Referring now to FIG. 5, a step in fabricating a set of field effecttransistors is shown. A gate dielectric layer 502 is deposited over thenitrogen-containing layers 402/404 using a high-k dielectric material.This step may include an anneal that causes the dielectric material tocombine with the nitrogen-containing material. In general, a “high-k”dielectric material is one that has a dielectric constant k that ishigher than the dielectric constant of silicon dioxide (e.g., greaterthan about 3.9) at room temperature and atmospheric pressure. In oneembodiment, the least one gate dielectric layer is composed of a high-koxide such as, for example, hafnium dioxide, zirconium dioxide, aluminumoxide, titanium dioxide, lanthanum oxide, strontium titanium oxide,lanthanum aluminum oxide, yttrium oxide, and mixtures thereof. Otherexamples of high-k dielectric materials for the at least one gatedielectric layer include hafnium silicate, hafnium silicon oxynitride orcombinations thereof.

The gate dielectric layer 502 may be formed by any appropriate processincluding, e.g., chemical vapor deposition (CVD), physical vapordeposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam(GCIB) deposition. CVD is a deposition process in which a depositedspecies is formed as a result of chemical reaction between gaseousreactants at greater than room temperature (e.g., from about 25° C.about 900° C.). The solid product of the reaction is deposited on thesurface on which a film, coating, or layer of the solid product is to beformed. Variations of CVD processes include, but are not limited to,Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD), PlasmaEnhanced CVD (EPCVD), and Metal-Organic CVD (MOCVD) and combinationsthereof may also be employed. In alternative embodiments that use PVD, asputtering apparatus may include direct-current diode systems, radiofrequency sputtering, magnetron sputtering, or ionized metal plasmasputtering. In alternative embodiments that use ALD, chemical precursorsreact with the surface of a material one at a time to deposit a thinfilm on the surface. In alternative embodiments that use GCIBdeposition, a high-pressure gas is allowed to expand in a vacuum,subsequently condensing into clusters. The clusters can be ionized anddirected onto a surface, providing a highly anisotropic deposition.

Referring now to FIG. 6, a step in fabricating a set of field effecttransistors is shown. A gate metal 602 is deposited over the gatedielectric layer 502. The gate metal 602 may be any appropriateconducting metal including, but not limited to, tungsten, nickel,titanium, molybdenum, tantalum, copper, platinum, silver, gold,rubidium, iridium, rhodium, rhenium, and alloys that include at leastone of the aforementioned conductive elemental metals.

Referring now to FIG. 7, an alternative step in fabricating a set offield effect transistors is shown. In this embodiment, the two deviceshave different high-k gate dielectric materials 702 and 706 anddifferent gate metal materials 704 and 708. This may be used to providea dual gate stack, with different devices having markedly differentproperties tailored to their particular applications.

Referring now to FIG. 8, a method of forming a set of field effecttransistors is shown. Block 802 forms the contrasting semiconductorregion 202 on a semiconductor layer 104, with one of the twosemiconductor materials being a group IV semiconductor and the otherbeing a III-V semiconductor. Block 804 forms source and drain regions302 in the contrasting region 202, defining a contrasting semiconductorchannel 303, as well as source and drain regions 304 in thesemiconductor layer 104, defining the semiconductor channel 306.

Block 806 forms nitrogen-containing regions 402 and 404 on therespective contrasting channel regions 303 and 306. Block 806 mayperform any appropriate blocking or masking needed to accomplish this,in one exemplary embodiment creating dummy gates, filling in adielectric layer 406, and then removing the dummy gates. Block 806 thenperforms, for example, an ammonia anneal or nitrogen plasma treatment tocreate a layer of nitrogen-containing material on the surface of thechannels 303/306. Block 808 deposits the gate dielectric 502 over thenitrogen-containing layers 402/404 and block 810 forms a gate 602 overthe gate dielectric 502.

In an optional embodiment, the gate dielectric and gate materials may bedifferent in different devices, according to the design needs of thedevices. In this case, blocks 808 and 810 form the first gate dielectric702 and first gate 704, while blocks 812 and 814 form a second gatedielectric 706 and gate 708 respectively.

It is to be understood that the present invention will be described interms of a given illustrative architecture having a wafer; however,other architectures, structures, substrate materials and processfeatures and steps may be varied within the scope of the presentinvention.

It will also be understood that when an element such as a layer, regionor substrate is referred to as being “on” or “over” another element, itcan be directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “connected” or “coupled” to another element, it canbe directly connected or coupled to the other element or interveningelements may be present. In contrast, when an element is referred to asbeing “directly connected” or “directly coupled” to another element,there are no intervening elements present.

A design for an integrated circuit chip may be created in a graphicalcomputer programming language, and stored in a computer storage medium(such as a disk, tape, physical hard drive, or virtual hard drive suchas in a storage access network). If the designer does not fabricatechips or the photolithographic masks used to fabricate chips, thedesigner may transmit the resulting design by physical means (e.g., byproviding a copy of the storage medium storing the design) orelectronically (e.g., through the Internet) to such entities, directlyor indirectly. The stored design is then converted into the appropriateformat (e.g., GDSII) for the fabrication of photolithographic masks,which typically include multiple copies of the chip design in questionthat are to be formed on a wafer. The photolithographic masks areutilized to define areas of the wafer (and/or the layers thereon) to beetched or otherwise processed.

Methods as described herein may be used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

Reference in the specification to “one embodiment” or “an embodiment” ofthe present principles, as well as other variations thereof, means thata particular feature, structure, characteristic, and so forth describedin connection with the embodiment is included in at least one embodimentof the present principles. Thus, the appearances of the phrase “in oneembodiment” or “in an embodiment”, as well any other variations,appearing in various places throughout the specification are notnecessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”,“and/or”, and “at least one of”, for example, in the cases of “A/B”, “Aand/or B” and “at least one of A and B”, is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of both options (A andB). As a further example, in the cases of “A, B, and/or C” and “at leastone of A, B, and C”, such phrasing is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of the third listedoption (C) only, or the selection of the first and the second listedoptions (A and B) only, or the selection of the first and third listedoptions (A and C) only, or the selection of the second and third listedoptions (B and C) only, or the selection of all three options (A and Band C). This may be extended, as readily apparent by one of ordinaryskill in this and related arts, for as many items listed.

Referring now to FIG. 9, a step in fabricating an alternative embodimentof a set of field effect transistors is shown. The surfaces may becleaned with a compatible wet clean to remove, e.g., adventitiouscontaminants (organics, metals, particles, etc.). The wet clean removesany native oxides that may have formed on the surfaces that would resultin poorly controlled thickness and composition of the gate dielectrics.This embodiment produces a nitrogen-containing layer on only one of thedevices and branches off of FIG. 3 above, depositing a two-layer maskover the surface. The mask includes a first masking layer 902 and asecond masking layer 904 that have etch selectivity with respect to oneanother. In one particular example, the first masking layer 902 isformed from an aluminum oxide while the second masking layer 904 isformed from a silicon dioxide layer. In alternative embodiments, onlyone masking layer may be used or the layers may be formed fromalternative materials such as, e.g., silicon or germanium. The materialsare selected for wet-chemical etch compatibility. The two masking layers902/904 may be deposited by any appropriate process including, e.g.,CVD, PVD, ALD, and GCIB deposition.

Referring now to FIG. 10, a step in fabricating an alternativeembodiment of a set of field effect transistors is shown. A photoresist1006 is used to cover one of the device regions (in this case, the III-Vdevice) while the masking layers 902 and 904 are etched away in the areaabove the group IV region, leaving etched masking layers 1002 and 1004.Notably, while the mask is shown as covering the contrasting region(e.g., the III-V region) and exposing the base semiconductor layer 104(e.g., a group IV semiconductor), it should be understood that the maskmay instead be removed over the contrasting region 202. The etch may beperformed using an anisotropic etch, such as a reactive ion etch (RIE)with a subsequent application of a buffered oxide etch to clean residuesfrom the exposed surface.

Referring now to FIG. 11, a step in fabricating an alternativeembodiment of a set of field effect transistors is shown. Thephotoresist 1006 is stripped away and a wet etch is used to remove thetop masking layer 904. In the present example, where the top maskinglayer 904 is formed from silicon dioxide, a dilute hydrofluoric acidwash may be used to remove the top masking layer 904, leaving the bottommasking layer 902 exposed.

Referring now to FIG. 12, a step in fabricating an alternativeembodiment of a set of field effect transistors is shown. Anitrogen-containing layer 1204 is formed on a top surface of exposedchannel 306. The nitrogen-containing layer may be formed using, e.g., anammonia anneal, nitrogen plasma, etc. A mask 1202 is deposited over thedevice, with gaps over the exposed channel 306, to limit the effect ofthe nitrogen-containing layer formation to only the channel areas. Themask 1202 may be formed by any appropriate dielectric or insulatormaterial, such as a hardmask material or bulk dielectric. Materials forthe mask 1202 may include, e.g., silicon dioxide or silicon nitride. Themask 1202 may be formed by any appropriate process including, e.g.,forming a dummy gate, depositing a masking material, and then removingthe dummy gate.

Referring now to FIG. 13, a step in fabricating an alternativeembodiment of a set of field effect transistors is shown. The mask 1202is extended over the source and drain regions 302 around the contrastingsemiconductor channel 303 to form mask 1302. The mask 1302 may beextended by any appropriate process including, e.g., blocking theexisting mask 1202, forming a dummy gate, depositing dielectric, andremoving the dummy gate and blocking structure.

Referring now to FIG. 14, a step in fabricating an alternativeembodiment of a set of field effect transistors is shown. A gate stack1402 is formed over both channel regions 303/306. The gate stackincludes a high-k dielectric layer and a gate material, as described inFIG. 6 above. Alternatively, the gate stacks may be formed withdiffering gate dielectrics and gate materials, as described in FIG. 7above.

Referring now to FIG. 15, an alternative method of forming a set offield effect transistors is shown. Block 1502 forms the contrastingsemiconductor region 202 on a semiconductor layer 104, with one of thetwo semiconductor materials being a group IV semiconductor and the otherbeing a III-V semiconductor. Block 1504 forms source and drain regions302 in the contrasting region 202, defining a contrasting semiconductorchannel 303, as well as source and drain regions 304 in thesemiconductor layer 104, defining the semiconductor channel 306.

Block 1506 masks one device region. The masked region may be either thegroup IV semiconductor layer 104 or the contrasting semiconductor region202. The mask may be a mono-layer mask, a dual-layer mask, or any otherappropriate masking configuration. Block 1508 then forms anitrogen-containing layer 1204 on the unmasked channel using, e.g., anammonia anneal or a nitrogen plasma process.

The masking process depicted above in FIGS. 9-12 is specifically drawnto a single-mask flow, but a two-mask flow is also possible. In the twomask process, block 1509 forms a mask over the nitrogen-containing layer1204, providing an opportunity to remove the remaining mask over theun-nitrided region. Block 1510 removes that mask and any other masks toexpose the channel regions.

Block 1512 deposits a gate dielectric 502 over the channel regions andblock 1514 forms a gate over the gate dielectric. In an optionalembodiment, the gate dielectric and gate materials may be different indifferent devices, according to the design needs of the devices. In thiscase, blocks 1512 and 1514 form a first gate dielectric and first gate,while blocks 1516 and 1518 form a second gate dielectric and gaterespectively.

Referring now to FIG. 16, a step in fabricating an alternativeembodiment of a set of field effect transistors is shown. Thisembodiment produces a nitrogen-containing gate dielectric layer andfollows FIG. 13 above. In this embodiment, the formation of anitrogen-containing layer directly on the channel is optional and may beomitted. A high-k dielectric material 1602 is formed on both channels byany appropriate deposition process, including CVD, PVD, ALD, or GCIB. Asnoted above, the high-k dielectric may be any appropriate dielectricmaterial having a dielectric constant that is greater than that ofsilicon dioxide.

Referring now to FIG. 17, a step in fabricating an alternativeembodiment of a set of field effect transistors is shown. The high-kdielectric layer 1602 is exposed to a nitriding process, such as anammonia anneal or a nitrogen plasma, to form a nitrogen-containinghigh-k layer 1702. As shown, the nitrogen-containing high-k may beapplied to only one of the devices, or alternatively may be applied toboth types of device.

Referring now to FIG. 18, a step in fabricating an alternativeembodiment of a set of field effect transistors is shown. Gate material1802 is deposited over the high-k dielectric 1602 and thenitrogen-containing high-k dielectric material 1702.

Referring now to FIG. 19, an alternative method of forming a set offield effect transistors is shown. Block 1902 forms the contrastingsemiconductor region 202 on a semiconductor layer 104, with one of thetwo semiconductor materials being a group IV semiconductor and the otherbeing a III-V semiconductor. Block 1904 forms source and drain regions302 in the contrasting region 202, defining a contrasting semiconductorchannel 303, as well as source and drain regions 304 in thesemiconductor layer 104, defining the semiconductor channel 306.

As noted above, the formation of a nitrogen-containing layer on one ormore of the channel regions is optional in this embodiment. Block 1906forms a mask 1002 on one device region while block 1908 forms thenitrogen-containing layer 1204 on the unmasked channel region. Block1910 then removes the mask 1002 to expose the un-nitrided channelregion.

Block 1912 forms a gate dielectric 1602 over the channel region(s), withone channel region being masked if the gate dielectrics will bedifferent between the devices. Block 1914 then masks one device region(assuming the dielectric layer 1602 was deposited over both devices) andblock 1916 forms a nitrogen-containing layer 1702 in the exposed gatedielectric to form a nitrogen-containing gate dielectric layer 1702.Block 1918 removes the mask protecting the un-nitrided gate dielectric1602 (if any) and block 1920 forms a gate 1802.

As above, in an optional embodiment, different devices may employdifferent gate dielectric materials and gate materials. In thisembodiment, block 1912 did not form a gate dielectric over both devices(using whatever form of masking is appropriate to the process at hand).Block 1922 therefore masks the nitrided device region and forms thesecond gate dielectric while block 1924 forms the second gate andremoves any remaining masks.

Having described preferred embodiments of patterned gate dielectrics forIII-V-based CMOS circuits (which are intended to be illustrative and notlimiting), it is noted that modifications and variations can be made bypersons skilled in the art in light of the above teachings. It istherefore to be understood that changes may be made in the particularembodiments disclosed which are within the scope of the invention asoutlined by the appended claims. Having thus described aspects of theinvention, with the details and particularity required by the patentlaws, what is claimed and desired protected by Letters Patent is setforth in the appended claims.

What is claimed is:
 1. A method for forming a plurality of semiconductor devices, comprising: forming a first channel region on a first semiconductor material; forming a trench from the first semiconductor material; forming a second channel region by filling the trench with a second semiconductor material, wherein a sidewall of the first semiconductor material is in contact with the second semiconductor material; and forming a gate one or more of the first channel region and the second channel region.
 2. The method of claim 1, wherein the first semiconductor material is one of a group IV semiconductor and a III-V semiconductor and wherein the second semiconductor material is the other of the group IV semiconductor and the III-V semiconductor and wherein the first channel region is coplanar with the second channel region.
 3. The method of claim 1, further comprising forming a channel nitrogen-containing layer on one or more of the first channel region and the second channel region before forming the gate.
 4. The method of claim 3, wherein forming the channel nitrogen-containing layer comprises forming the channel nitrogen-containing layer on only one of the first channel region and the second channel region.
 5. The method of claim 3, wherein forming the channel nitrogen-containing layer comprises forming the channel nitrogen-containing layer on both the first channel region and the second channel region.
 6. The method of claim 1, wherein forming the nitrogen-containing layer comprises treating a surface of the gate to form a nitrogen-containing gate dielectric layer.
 7. The method of claim 6, wherein forming the nitrogen-containing layer comprises one of performing an ammonia anneal and exposing the dielectric layer to a nitrogen plasma.
 8. The method of claim 1, further including forming a gate dielectric, wherein forming the gate comprises forming a first gate dielectric layer and a first gate over only one of the first channel region and the second channel region, further comprising: forming a second gate dielectric layer on the other of the first channel region and the second channel region, wherein the second gate dielectric layer is formed from a dielectric material different from the material of the first gate dielectric layer; and forming a second gate on the second dielectric layer, wherein the second gate is formed from a gate material different from the material of the first gate.
 9. A method for forming a plurality of semiconductor devices, comprising: forming a first channel region on a first semiconductor material; forming a trench within the first semiconductor material; forming a second channel region by filling the trench with a second semiconductor material different from the first semiconductor material, wherein a sidewall of the first semiconductor material is in contact with the second semiconductor material; and forming a gate on a gate dielectric including a nitrogen-containing layer in one or more of the first channel region and the second channel region.
 10. The method of claim 9, wherein the first semiconductor material is one of a group IV semiconductor and a III-V semiconductor and wherein the second semiconductor material is the other of the group IV semiconductor and the III-V semiconductor and wherein the first channel region is coplanar with the second channel region.
 11. The method of claim 9, further comprising forming a channel nitrogen-containing layer on one or more of the first channel region and the second channel region before forming the gate dielectric layer.
 12. The method of claim 11, wherein forming the channel nitrogen-containing layer comprises forming the channel nitrogen-containing layer on only one of the first channel region and the second channel region.
 13. The method of claim 11, wherein forming the channel nitrogen-containing layer comprises forming the channel nitrogen-containing layer on both the first channel region and the second channel region.
 14. The method of claim 9, wherein forming the nitrogen containing layer comprises treating a surface of the gate dielectric to form a nitrogen containing gate dielectric layer.
 15. The method of claim 14, wherein forming the nitrogen-containing layer comprises one of performing an ammonia anneal and exposing the one or more regions to a nitrogen plasma.
 16. The method of claim 9, further including forming a gate dielectric, wherein forming the gate on the gate dielectric comprises forming a first gate dielectric layer and a first gate over only one of the first channel region and the second channel region, further comprising: forming a second gate dielectric layer on the other of the first channel region and the second channel region, wherein the second gate dielectric layer is formed from a dielectric material different from the material of the first gate dielectric layer; and forming a second gate on the second dielectric layer, wherein the second gate is formed from a gate material different from the material of the first gate.
 17. A semiconductor device, comprising: a first channel region formed from a first semiconductor material; a second channel region formed by removing a portion of the first semiconductor material from the second semiconductor region to form a trench, and filling the trench with a second semiconductor material, wherein a sidewall of the first semiconductor material is in contact with the second semiconductor material; and a gate formed over one or more of the first channel region and the second channel region.
 18. The semiconductor device of claim 17, wherein the first semiconductor material is one of a group IV semiconductor and a III-V semiconductor and wherein the second semiconductor material is the other of the group IV semiconductor and the III-V semiconductor.
 19. The semiconductor device of claim 17, further comprising a gate dielectric layer, wherein a nitrogen-containing layer is formed on the top surface of the gate dielectric layer.
 20. The semiconductor device of claim 17, wherein the nitrogen-containing layer is formed on only the first channel region and the gate comprises a first gate over the second channel region, further comprising: a first gate dielectric layer formed over the first channel region, under the first gate; a second gate dielectric layer formed over the second channel region from a dielectric material different from the dielectric material of the first gate dielectric layer; and a second gate formed on the second gate dielectric layer from a gate material different from the gate material of the first gate. 